The present invention relates generally to semiconductor devices and methods for forming the such devices. More particularly, the present invention is directed to metal gate structures that provide a practical way of device integration.
Complementary metal-oxide-semiconductor (CMOS) circuits are becoming more highly integrated and the individual devices which combine to form a CMOS circuit are becoming increasingly smaller. With the continued scaling of CMOS devices down to sub 100 nm gate lengths and beyond, the silicon dioxide (SiO2) or xe2x80x9coxidexe2x80x9d conventionally used as a gate dielectric has been correspondingly reduced to thicknesses of less than 20 angstroms (xc3x85).
However, device scaling based on polysilicon gate scaling and gate oxide thickness reduction is seriously challenged as the thickness of the gate oxide is scaled below 20 xc3x85. The gate leakage currents, determined by quantum-mechanical direct tunneling through these thin oxides, reach intolerably high limits for these ultra-thin gate dielectrics. For example, current densities greater than 1 amp/cm2 are typical for gate oxides having thicknesses in the 15-17 xc3x85 range. Also, dopant diffusion from the polysilicon gate seriously limits further scaling of SiO2 based gate dielectrics because the thinner gate oxide is more vulnerable to dopant penetration.
A metal gate can eliminate the dopant penetration problem. With the metal gate, the poly depletion effect can be eliminated and the same electrical performance can be obtained even with a thicker gate oxide. Typical poly depletion increases electrical thickness of the gate oxide by 4-6 xc3x85. Thus, leakage current can be reduced by one to two orders of magnitude compared to a polysilicon gate at the same electrical thickness.
Leakage current can be further reduced by using alternative gate dielectrics. These alternative gate dielectrics are chosen to have higher permittivity values than silicon dioxide. Dielectric films having permittivities, or dielectric constants (K), higher than silicon dioxide are referred to as high-K dielectric films. When these high-K dielectric films are used as gate dielectric films, the physical thickness of the gate dielectric can be large while the electrical equivalent thickness relative to SiO2 can be scaled for compatibility with the other reduced feature sizes. The thickness (teq) of a high-dielectric constant film, for example, may be calculated by the formula:
teq=tphy(xcex5SiO2/xcex5high-K) 
where tphy is the actual thickness of the substitute film and xcex5SiO2 and xcex5high-K are the dielectric constants of SiO2 and the high-K dielectric film, respectively.
However, recent research has shown that these high-k dielectrics like ZrO2 and Al2O3 have poor compatibility with a polysilicon gate, while some metal electrodes have shown very good compatibility with high-K dielectrics. The high-K dielectric gate materials, which are becoming favored as gate dimensions shrink, generally cannot withstand high-temperature ( greater than 600xc2x0 C.) processing after they are deposited onto a silicon substrate. Therefore, the use of polysilicon, which must be formed and doped using high-temperature processing, is restricted or precluded when a high-K dielectric gate material is used.
Lower leakage current, and freedom from dopant penetration and poly depletion effect can be significant advantages for pursuing a metal electrode. The predominant gate material for CMOS devices seems to have been doped polysilicon which enables the formation of dual work function devices needed for CMOS. Dual work function devices are produced by doping the polysilicon gates differently depending on the specific device. A dual work function is required because CMOS devices include both N-channel transistors, also known as NFET (N-channel Field Effect Transistors), and P-channel transistors, also known as PFET (P-channel Field Effect Transistors). N-channel and P-channel transistors formed within the same device operate at different threshold voltages. The threshold voltage of a transistor is directly related to the work function of the gate material.
For a seamless transition from use of a polysilicon gate to a metal gate, two different metal electrodes with workfunctions similar to n+poly and p+poly are desired. See, for example, xe2x80x9cMetal Gates for Advanced CMOS Technology,xe2x80x9d by Maiti et al., SPIE Conference on Microelectronic Device Technology III, Santa Clara, Calif. (SPIE Vol. 3881, September 1999, pgs. 46-57), U.S. Pat. No. 6,291,282, METHOD OF FORMING DUAL METAL GATE STRUCTURES OR CMOS DEVICES, Wilk, et al., Sep. 18, 2001, and FIS9-1999-0250US1, D. A. Buchanan, D. Neumayer, and P. R. Varekamp, xe2x80x9cCMOS Metal High K Gate Device and Methodxe2x80x9d, Ser. No. 09/592,031, Filed Jun. 12, 2000, which are all incorporated herein by reference. However, the present inventors believe that conventional CMOS technology is not readily compatible with gate electrodes formed of two different materials (e.g., metals), because two different metal gate electrodes cannot be readily connected electrically if a conventional CMOS process is used.
The present invention provides an integration method to build a dual workfunction CMOS device with metal gate electrodes.
The present invention provides a structure and method for providing metal gate electrodes which are compatible with CMOS transistors. The metal gate electrode is a composite structure which includes a bulk metal film and a thin metal layer or metal alloy layer. The layer includes/exhibits a particular work function chosen in conjunction with the desired VT of the transistor being formed. With respect to CMOS devices having both P-channel and N-channel transistors, the present invention provides a semiconductor device including a P-channel transistor having a first metal gate formed of a first composite film including a bulk metal film formed over a first metal layer having a first work function, and an N-channel transistor having a second metal gate formed of a second composite film including the bulk metal film formed over a second metal layer having a second work function which is different from the first work function. Each of the first metal layer and second metal layer is chosen to produce a desired threshold voltage, VT, for the respective transistor. According to an essential aspect of the present invention, the bulk metal film suitably electrically connects the first metal layer to the second metal layer.
The present invention also includes a method to connect the two different metals. In this method, two metal gates are formed locally in trench-shaped gates which are recessed using a wet etch or a reactive ion etch. A bulk metal electrode is filled into the recessed trench region. In this method, the bulk metal electrode (e.g., film) is not necessarily the same composition as the two initial metal electrodes.
It is to be understood that the foregoing brief description and the following detailed description are intended to be exemplary, not restrictive, of the present invention.